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 HD74LV574A
Octal D-type Flip-Flops with 3-state Outputs
REJ03D0520-0100 Rev.1.00 Feb. 01, 2005
Description
The HD74LV574A has eight edge trigger D type flip flops with three state outputs in a 20 pin package. Data at the D inputs meeting set up requirements, are transferred to the Q outputs on positive going transitions of the clock input. When the clock input goes low, data at the D inputs will be retained at the outputs until clock input returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
* * * * * * * VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25C) Output current 8 mA (@VCC = 3.0 V to 3.6 V), 16 mA (@VCC = 4.5 V to 5.5 V) Ordering Information
Part Name HD74LV574AFPEL HD74LV574ATELL Package Type SOP-20 pin (JEITA) TSSOP-20 pin Package Code (Previous Code) PRSP0020DD-B (FP-20DAV) PTSP0020JB-A (TTP-20DAV) Package Abbreviation FP T Taping Abbreviation (Quantity) EL (2,000 pcs/reel) ELL (2,000 pcs/reel)
Function Table
Inputs OE H L L L Note: H: High level L: Low level X: Immaterial Z: High impedance Q0: Output level before the indicated steady state input conditions were established. CLK X D X L H X Output Q Z L H Q0
Rev.1.00 Feb. 01, 2005 page 1 of 7
HD74LV574A
Pin Arrangement
OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10
DQ
20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 CLK
DQ
DQ
DQ
DQ
DQ
DQ
DQ
(Top view)
Absolute Maximum Ratings
Item Supply voltage range Input voltage range*
1
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 -0.5 to 7.0 -20 50 35 70 835 757 -65 to 150
Unit V V V mA mA mA mA mW C SOP TSSOP
Conditions
Output voltage range*1, 2 Input clamp current Output clamp current Continuous output current Continuous current through VCC or GND Maximum power dissipation at Ta = 25C (in still air)*3 Storage temperature
Output: H or L VCC: OFF or Output: Z VI < 0 VO < 0 or VO > VCC VO = 0 to VCC
Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150C.
Rev.1.00 Feb. 01, 2005 page 2 of 7
HD74LV574A
Recommended Operating Conditions
Item Supply voltage range Input voltage range Output voltage range Output current Symbol VCC VI VO IOH Min 2.0 0 0 0 -- -- -- -- IOL -- -- -- -- Input transition rise or fall rate t /v 0 0 0 Operating free-air temperature Ta -40 Note: Unused or floating inputs must be held high or low. Max 5.5 5.5 VCC 5.5 -50 -2 -8 -16 50 2 8 16 200 100 20 85 C ns/V A mA A mA Unit V V V H or L High impedance state VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V Conditions
DC Electrical Characteristics
Ta = -40 to 85C
Item Input voltage Symbol VIH VCC (V)* 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 VIL 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Output voltage VOH Min to Max 2.3 3.0 4.5 VOL Min to Max 2.3 3.0 4.5 Input current Off-state output current Quiescent supply current Output leakage current Input capacitance IIN IOZ ICC IOFF CIN 0 to 5.5 5.5 5.5 0 3.3 Min 1.5 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- -- VCC - 0.1 2.0 2.48 3.8 -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2.9 Max -- -- -- -- 0.5 VCC x 0.3 VCC x 0.3 VCC x 0.3 -- -- -- -- 0.1 0.4 0.44 0.55 1 5 20 5 -- A A A A pF V IOH = -50 A IOH = -2 mA IOH = -8 mA IOH = -16 mA IOL = 50 A IOL = 2 mA IOL = 8 mA IOL = 16 mA VIN = 5.5 V or GND VO = VCC or GND VIN = VCC or GND, IO = 0 VI or VO = 0 to 5.5 V VI = VCC or GND Unit V Test Conditions
Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions.
Rev.1.00 Feb. 01, 2005 page 3 of 7
HD74LV574A
Switching Characteristics
VCC = 2.5 0.2 V
Ta = 25C Item Maximum clock frequency Propagation delay time Enable time Disable time Setup time Hold time Pulse width Symbol tmax tPLH tPHL tZH tZL tHZ tLZ tSU th tw Min 60 50 -- -- -- -- -- -- 5.5 2.0 7.0 Typ 105 85 9.7 11.8 8.9 10.9 6.3 8.2 -- -- -- Max -- -- 16.6 19.6 16.1 19.0 12.8 17.5 -- -- -- Ta = -40 to 85C Min 50 40 1.0 1.0 1.0 1.0 1.0 1.0 5.5 2.0 7.0 Max -- -- 20.0 23.0 19.0 22.0 15.0 20.0 -- -- -- ns ns ns ns ns ns Unit MHz Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF Data before CLK Data after CLK CLK: "H" or "L" OE Q OE Q CLK Q FROM (Input) TO (Output)
VCC = 3.3 0.3 V
Ta = 25C Item Maximum clock frequency Propagation delay time Enable time Disable time Setup time Hold time Pulse width Symbol tmax tPLH tPHL tZH tZL tHZ tLZ tSU th tw Min 80 55 -- -- -- -- -- -- 3.5 1.5 5.0 Typ 150 110 6.8 8.3 6.3 7.7 4.7 5.9 -- -- -- Max -- -- 13.2 16.7 12.8 16.3 13.0 15.0 -- -- -- Ta = -40 to 85C Min 70 50 1.0 1.0 1.0 1.0 1.0 1.0 3.5 1.5 5.0 Max -- -- 15.5 19.0 15.0 18.5 15.0 17.0 -- -- -- ns ns ns ns ns ns Unit Test Conditions CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF Data before CLK Data after CLK CLK: "H" or "L" OE Q OE Q CLK Q FROM (Input) TO (Output)
MHz CL = 15 pF
VCC = 5.0 0.5 V
Ta = 25C Item Maximum clock frequency Propagation delay time Enable time Disable time Setup time Hold time Pulse width Symbol tmax tPLH tPHL tZH tZL tHZ tLZ tSU th tw Min 130 85 -- -- -- -- -- -- 3.5 1.5 5.0 Typ 205 170 4.9 5.9 4.6 5.5 3.4 4.0 -- -- -- Max -- -- 8.6 10.6 9.0 11.0 9.0 10.1 -- -- -- Ta = -40 to 85C Min 110 75 1.0 1.0 1.0 1.0 1.0 1.0 3.5 1.5 5.0 Max -- -- 10.0 12.0 10.5 12.5 10.5 11.5 -- -- -- ns ns ns ns ns ns Unit MHz Test Conditions CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF CL = 15 pF CL = 50 pF Data before CLK Data after CLK CLK: "H" or "L" OE Q OE Q CLK Q FROM (Input) TO (Output)
Rev.1.00 Feb. 01, 2005 page 4 of 7
HD74LV574A
Output-skew Characteristics
CL = 50 pF
Ta = 25C Item Output skew Symbol tsk (O) VCC = (V) 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min -- -- -- Max 2.0 1.5 1.0 Ta = -40 to 85C Min -- -- -- Max 2.0 1.5 1.0 Unit ns
Note: Skew between any outputs of the same package switching in the same direction. This parameter is warranted but not production tested.
Operating Characteristics
CL = 50 pF
Ta = 25C Item Power dissipation capacitance Symbol CPD VCC = (V) 3.3 5.0 Min -- -- Typ 21.1 22.8 Max -- -- Unit pF Test Conditions f = 10 MHz
Noise Characteristics
CL = 50 pF
Ta = 25C Item Quiet output, maximum dynamic VOL Quiet output, minimum dynamic VOL Quiet output, minimum dynamic VOH High-level dynamic input voltage Low-level dynamic input voltage Symbol VOL (P) VOL (V) VOH (V) VIH (D) VIL (D) VCC = (V) 3.3 3.3 3.3 3.3 3.3 Min -- -- -- 2.31 -- Typ 0.6 -0.5 2.9 -- -- Max 0.8 -0.8 -- -- 0.99 Unit V V V V V Test Conditions
Test Circuit
Output 1 k CL TEST t PLH /t PHL t ZH/t HZ t ZL /t LZ OPEN GND VCC S2 OPEN GND VCC
S2
Note: C L includes the probe and jig capacitance.
Rev.1.00 Feb. 01, 2005 page 5 of 7
HD74LV574A
* Waveform - 1
Input CLK tr 90 % 90 % 50 %VCC 10 % tr 90 % 10 % t PLH Output Q 50 %VCC tr 90 % 90 % 50 % 50 % VCC VCC tw th tf VCC 50 %VCC 10 % tw GND VCC Input D 50 %VCC 50 %VCC GND 50 %VCC 10 % tf 90 % 10 % t PHL 50 %VCC VOL GND VCC tf VCC
Input D
GND VOH
* Waveform - 2
Input CLK 10 % tsu
* Waveform - 3
Input OE
tf 90 % 50 %VCC 10 % t ZL
tr 90 % 50 %VCC 10 % t LZ VCC GND VCC
Waveform - A
50 %VCC t ZH t HZ 50 %VCC
VOL + 0.3 V VOH - 0.3 V
VOL VOH GND
Waveform - B
Notes: 1. tr 3 ns, tf 3 ns 2. Input waveform: PRR 1 MHZ, duty cycle 50% 3. Waveform-A is for an output with internal conditions such that the output is low except when disabled by the output control. 4. Waveform-B is for an output with internal conditions such that the output is high except when disabled by the output control.
Rev.1.00 Feb. 01, 2005 page 6 of 7
HD74LV574A
Package Dimensions
JEITA Package Code P-SOP20-5.5x12.6-1.27 RENESAS Code PRSP0020DD-B Previous Code FP-20DAV MASS[Typ.] 0.31g
*1
D 11
F
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
20
bp
E
HE
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 12.60 5.50 Max 13.0
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2 A1 0.00
10 bp x M L1
0.10
0.20 2.20
A bp b1 c c
1
0.34
0.40
0.46
0.15
0.20
0.25
A
q
HE
0 7.50 7.80 1.27
8 8.00
q
y
e x y
A1
L
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
JEITA Package Code P-TSSOP20-4.4x6.5-0.65
RENESAS Code PTSP0020JB-A
Previous Code TTP-20DAV
MASS[Typ.] 0.07g
*1
D F 11
20
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
*2
E
c
Reference Symbol
Dimension in Millimeters Min Nom 6.50 4.40 Max 6.80
Index mark
Terminal cross section ( Ni/Pd/Au plating )
D E A2 A1 0.03
0.07
0.10 1.10
1 Z e
*3
10 bp L1 x M
A bp b1 c c1 0.10 0.15 0.15 0.20
0.25
0.20
q
A
HE
0 6.20 6.40 0.65
8 6.60
q
A1
L y
e x y
0.13 0.10 0.65 0.4
1
Detail F
Z L L 0.5 1.0
0.6
Rev.1.00 Feb. 01, 2005 page 7 of 7
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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Colophon .2.0


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